High frequency parametric voltage regulator

ABSTRACT

A parametric regulator in which an inverter is positioned between the input source of power and a parametric device to provide the parametric device with a high frequency input. The output of the parametric device is rectified and monitored by a sensing circuit which controls the frequency of the inverter to maintain the output voltage constant. A sensing and control circuit is provided which permits the use of conventional transistors in the inverter by establishing a proper timing pattern for the triggering of these transistors into and out of conduction.

I United States Patent 1151 3,679,962 Wanlass [4 1 July 25, 1972 54]HIGH FREQUENCY PARAMETRIC 3,413,538 11/1968 Hodges..

VOLTAGE REGULATOR 3,461,374 8/1969 Rhyne 3,490,027 l/l970 Galetto et al...321/2 [72] Inventor: Cravens L. Wanlnss, Santa Ana, Calif. AssigneezAmbac Ind ,eslncorponted FOREIGN PATENTS OR APPLICATIONS l Filed: J 19701,064,748 4/1967 Great Britain 32 /18 [21] AWL N05 871,477 OTHERPUBLICATIONS IBM Technical Disclosure Bulletin, Regulated Power Sup-Relmd 9m ply" v01. 7, No. 10, p. 967, March 1965 [63]Continuation-in-part of Ser. No. 771,8l6, Oct. 30, pmfieedinfis ofNation?! Conference, The

1968 netic Cross Valve and 1ts Applicatlon to Subfrequency Power IGeneration," Vol. 5, pp. 450-466, 1949 [52] [1.8. CI ...32l/1l8, 321/2,33221192656 Primary Examiner wimam H. Beha, Jr. 51] 1111. c1. ..1102m7/52, 005: [58] FieldolSearch ..32l/2, ll, 18, 25,45 R, 45 S;

323/60 [57] ABSTRACT A parametric regulator in which an inverter ispositioned [56] Reference Cited between the input source of power and aparametric device to provide the parametric device with a high frequencyinput. UNITED STATES PATENTS The output of the parametric device isrectified and monitored by a sensing circuit which controls thefrequency of the inverter to maintain the output voltage constant. Asensing and I control circuit is provided which permits the use ofconven- 3,559,032 l/ 1971 tional transistors in the inverter byestablishing a proper tim- 3,243,686 3/1966 ing pattern for thetriggering of these transistors into and out 3,341,766 9/1967ofconduction. 3,371,263 2/1968 3,403,323 9/1968 Wanlass ..323/60 UX 3Claims, 6 Drawing Figures FZ/LM/A V6 z/ L m/z/eerae 46 E66 M765 (6.30/46) A /a& a2 53 37' SMET/NG 35 55 0660/7 v1 25 55 our/ ar VOCZ4656/1/5/A/6 C/ZCU/T 36 HIGH FREQUENCY PARAMETRIC VOLTAGE REGULATORCROSS-REFERENCE TO OTHER APPLICATIONS This is ,acontinuation-impartapplication of my application- Ser. No. 771,816,filed Oct. 30, 1968,,now abandoned.

In UnitedStates patent application Ser. No. 589,780, filed Oct. 25,l966'now abandoned), and its continuation-impartapplication, Ser. No.821,933, filed Mayv 5, 1,969, by Leslie Kent Wanlass, and each assignedto the assignee, of the present application, there is disclosed .avoltage regulator. employing a parametric circuit for providing aregulated output voltage from an unregulated AC input voltage.Theparametric circuit in that application comprises an L-C circuit, theself-inductance of the load winding component'of-which is a variableinductor device of the type disclosed, in US. Pat. No. 3,403,323 toLeslie Kent Wanlass, and also assigned to the assignee of the presentapplication. The theoretical considerations and operating principles ofthis variableinductor and of the parametric circuit are described indetail in that applicaw tion and that patent, the disclosures of whichare incorporated by reference herein.

Briefly, the variable inductor disclosediin U.S; Pat. No. 3,403,323comprises a magnetic corehaving a pair of windings thereon. The core isconstructed so that it has-four common regions or legs and two end orjoining portions for magnetically coupling the common regions. The coilsare wound on the end portions with their axes displacedat 90 so thatnormally there is no inductive coupling, between them, and so that. theflux componentsgenerated as a result of passing currents throughthe twowindings are at all times inv opposing relationshipin two of the legsandanadditiverelationship in the other two legs. As a result of thisconstruction, current in one of the windings, referred to asthecontrol'winding, generates a magnetic flux which controlsthereluctanceof. the magnetic circuit encompassed by the. second. winding,v referredto as the load winding, in such a manner thatvariations in this fluxcaused by variations in the currentin the control winding cause thehysteresis loop of. the magnetic circuit encompassed by the loadwindingto be efiectively rotated; thereby varyingthe inductance of theload winding. Because of the construction of the device, the inductancevaries at twice the frequency ofv an alternating current applied to thecontrol winding. I

Thisphenomenon is utilized intheparametriccircuit disclosed inapplication Ser. No..589,780 (now abandoned) and its continuation-impartapplication, Ser. No. 821,933. The parametric devices disclosed in thoseapplications andein this one differ from those shownin U.S. Pat. No.3,403,323 in a number of respects which together distinguish parametricdevices.

SUMMARY OF THE INVENTION.

The following aredifferences between the parametric device ofapplication Ser. No. 821,933 and the presenti'nvention and devices ofUS. Pat. No. 3,403,323, capacitor is coupled to the load winding of thevariable inductor to form-energy storage or tank circuit, which isnormally a resonant circuit. Energy is transferred to the resonant ortank circuit by. pumping the control winding with an alternating currentofthe same frequency as that to which the resonant or. tank circuit istuned, thatis, the output frequency. Once the parametric circuit buildsupto its stable oscillating point,,variations in magnitude of thepumping source do not appreciably. effect its output. Therefore, bycoupling the line to be regulated to the control winding of theinductance device, a regulated, almost perfect sine wave,,displaced 90in phase with the input, can be taken from the resonant or tank circuit.Since there is no direct transformer coupling between the windings,.thedevice serves as a bilateral filter, removing transients and noisegenerated in either the line or the load.

While, the described. parametric regulator is extremely satisfactorywhere the-frequency of the input voltage is relatively constant, itsoutput is frequency sensitive. The output is also to some extentsensitive to changes in load. Moreover, the regulator, while requiringless magnetic material than conventional devices, nevertheless requiresa substantial amount of copper to form the windings. The capacitor mustalso be ratherv sizable. The device'is therefore somewhat bulky, heavy,and expensive.

Common to. the variable inductor of U.S. Pat. No. 3,402,323,, butdifferent from other prior art is the characteristic variation-ofself-inductance at, twice the frequency applied-.to the controlwindingof the parametric device which produces an outputfrequency in the loadwinding the same as theinputfrequency.

According-to the present invention, aclosed loop parametric regulator isprovided which. is not sensitive to either frequency. or'loadchanges. Inaddition, the amount of mag netic material and windings required isgreatly reduced, as is the size of thecapacitor necessary. Consequently,the circuit is compact, lightweight and inexpensive. These advantagesare obtained by'converting the'input voltage to be regulated to a highfrequency voltage by means of an inverter or the like and applying theoutputof the inverter to a parametric device of the type described. Theuse of the high frequency input permits a substantial,reductioninthesize and weight of the core and'in' the number of turns required, and inthe size of the capacitor required. The closed loop feature is providedby sensing the output voltage and controlling the frequency oftheinverter in accordance therewith.

The closed loop operation of the present invention is also easilyconstructed to permit the system to achieve even better performance..Forexample, a typical inverter circuit exhibits a large'switching powerloss because of. the fact that a conducting element such as a transistorhas a delay associated with its turnoff while the, non-conductingelement has no substantial delay associated with its turn on.Consequently, both elements can be conducting at the same time resultingin a high short circuitcurrent and substantial power loss. In addition,these elements generally have a poor frequency response so that there.is a significant switching time even after the delay is over..The-shortcircuit currents often burn out the transistors or significantly reducetheir life, as well as reduce the efficiency ofthe circuit.

To overcome these problems, special high frequency transistors withminimumdelay and switching time are em.- ployed. These transistors are,however, very expensive. Because of the unique properties of theparametric device utilized in this invention, it is possible to use thecheaper transistorsand control them in such a manner that they do notsimultaneously conduct, i.e., by delayingthe turn on of thenon-conducting transistor until the conducting transistor is turned off.This is possible because of the insensitivity of the parametric deviceto the input wave shape of the input voltage..

Itistherefore anobject of the present invention to provide a closedlloopparametric voltage regulator which is compact, lightweight, efficientand'inexpensive.

It is also an object of the present invention to provide a closedloopparametric voltage regulator which is insensitive to changes in theinput frequency or any other parameter affecting-the output voltagevalue.

BRIEF DESCRIPTION'OF THE DRAWINGS FIG. 1 is a perspective view of avariable inductor useful in the voltage regulator of the presentinvention;

FIG. 2 is a schematic diagram of a first embodiment of a voltageregulator according to the present invention;

FIG. 3 is a schematic diagram of a second embodiment of a voltageregulator according to the present invention;

FIGS. 4 and 5 are schematic circuit diagrams of portions ofthe'embodiment of FIG. 3; and

FIG. 6 is a timing diagram showing the various waveforms present in theembodiment of FIGS. 3, 4 and 5.

DESCRIPTION OF EMBODIMENTS OF THE INVENTION I In the drawings, theconvention adopted in the aforementioned patent and application forindicating a core according to the teachings of U.S. Pat. No. 3,403,323are followed, that is, such a core as indicated by the use of a T-shapediron symbol. While any of the various core structures illustrated anddescribed in that patent could be used in this invention, the preferredconstruction is similar to that shown in FIG. 7 of the patent. Aninductor utilizing such a core is shown in FIG. 1. The inductor 10comprises a core made up of two C-cores I1 and 12, rotated 90 degreesfrom each other and joined at their bases, as shown in FIG. 1. The core11 has a winding 13 wound thereon while the core 12 has a winding 14wound thereon, the windings 13 and 14 being preferably at right angles.

Turning now to FIG. 2, an unregulated AC input voltage is applied toinput terminals 16 and 17. These terminals are connected by conductorsl8 and 19 to a full wave rectifier 20, the output of which is filteredby a capacitor 21 and applied to an inverter 22 by lines 23 and 24. Theinverter can be of any conventionaltype, such as those employing siliconcontrolled rectifiers or transistors which serves to produce analternating current output, typically in square waveform, in response toa direct current input. The circuitry of the inverter is not illustratedor described as such circuits are well known to those skilled in theart. The output frequency of the inverter 22 may, for example, bekilocycles per second. If desired, a suitable frequency converter may beused in place of the rectifier 20 and inverter 22.

The output of the inverter 22 is applied to the control winding 13 of avariable inductor such as that shown at 10 in FIG. 1. The output or loadwinding 14 of the variable inductor 10 is connected in parallel with acapacitor 25 to form a resonant or tank circuit tuned to the outputfrequency of the inverter 22. The load winding 14 has a center tap whichis connected by a line 26 to an output terminal 27. The other outputterminal 28 is connected through diodes 29 and 30 to taps 31 and 32 onthe winding 14 so that the output is a direct current voltage. Afiltering capacitor 33 is connected across the output terminals 27 and28.

The output voltage across the terminals 27 and 28 is applied to anoutput voltage sensing circuit 34 by lines 35 and 36. The output voltagesensing circuit 34 may be any conventional type which compares theoutput voltage with a reference voltage and produces a control voltagerepresentative of any deviation of the output voltage from thereference. It may, for

example, be similar to that disclosed in my US Pat. No. 3,409,822. Theoutput of the sensing circuit 34 is applied by lines 37 and 38 to theinverter 22 and serves to vary the frequency of the output waveform ofthe inverter 22 if the output voltage differs from the reference voltageestablished in the sensing circuit 34.

A starting circuit 39 is coupled across the lines 23 and 24 by lines 40and 41. The output of the starting circuit is connected to the lines 37and 38 and hence to the inverter 22. The purpose of the starting circuitis to permit the parametric circuit to be self-starting by reducing theoutput frequency of the inverter 22 to increase its input current sothat sufficient coupling is established between the windings l3 and 14to initiate oscillations in the parametric device in the mannerdescribed in the aforementioned application Ser. No. 589,780. Thestarting circuit 39 may simply comprise a capacitor and diode for thispurpose as will be obvious to those skilled in the art. Of course, otherstarting mechanisms could be provided in place of the starting circuit39 if desired.

The operation of the circuit shown in FIG. 2 is basically similar tothat disclosed in the aforementioned applications Ser. Nos. 589,780 and821,933. The primary difference, of course, is that the frequency of theinput to the parametric device, and the frequency to which the tankcircuit made up of the winding 14 and capacitor 41 is tuned, are muchhigher than conventional power frequencies. The use of such a higherfrequency permits the size of the core and the number of turns of thewindings to be greatly reduced. Since the magnitude of the outputvoltage of the parametric device is dependent upon the paraneters of theresonant circuit and upon the input frequency, it can be seen that theoutput voltage can be maintained constant by use of the sensing circuit34 which controls the frequency of the output of the inverter 22.Consequently, the regulator of the present invention is insensitive tochanges in line frequency and is also insensitive to changes in load orany other parameter which might effect the output voltage. This isaccomplished without losing any of the advantages, such as bilateralfiltering, which are inherent in the use of a parametric regulator ofthe type herein disclosed. Although the regulator is illustrated asoperating from an alternating current input, it will be obvious to thoseskilled in the art that the input voltage could be DC in which case therectifier 20 and capacitor 21 would not be necessary.

Turning now to FIG. 3, another embodiment of the regulator according tothe present invention is illustrated. In this embodiment, an unregulatedor substantially unregulated AC input voltage is applied to inputterminals 48 and 49 which are connected to a rectifier and filter 50.The output of the rectifier and filter 50 are connected to the input ofan inverter 51 the output of which is connected to the control winding52 of a variable inductor 53, preferably of the type described in theaforementioned patent. The load winding 54 of the inductor 53 isconnected with a capacitor 55 to form the tank circuit of a parametricdevice such as that disclosed in the aforementioned patent applicationSer. No. 589,780. The output of this tank circuit is applied to arectifier and filter 56 which is connected to output terminals 57 and58. v

A control amplifier and oscillator 59 is connected across the outputterminals 57 and 58. This control amplifier and oscillator serves toconvert the DC output voltage into a series of pulses, the frequency ofthe pulses being dependent upon the amplitude of the output DC voltage.Such a circuit is conventional, for example, in digital volt meters, andneed not be discussed further here. The output of the control amplifierand oscillator 59 is fed to a variable frequency drive and delay logic60 the output of which is a control signal which controls the operationof the inverter 51.

The output of the variable frequency drive and delay logic 60 causes theoutput of the inverter 51 to vary in frequency in response to variationsin the voltage appearing across output terminals 57 and 58. In otherwords, the operation of the conducting elements in the inverter 51 iscontrolled by the pulses generated in the control amplifier andoscillator 59 as modified in the variable frequency drive and delaylogic 60. The purpose of the latter circuit is to produce a train ofpulses that correspond in frequency with those produced by the controlamplifier and oscillator 59 but whose triggering edges are delayed sothat one of the conducting elements in the inverter 51 is completelyturned off before the alternate conducting element is turned on so as toeliminate the short circuit conditions discussed previously. As will beapparent, the elements 59, 60 and 51 of FIG. 3 are equivalent inoperation to the elements 34 and 22 of FIG. 2 with the additionalfeature that the pulses delivered to the inverter to control itsoperation are delayed in a desired manner. In all other respects, theoperation of the systems of FIG. 2 and FIG. 3 are similar.

Turning now to FIGS. 4 and 5, there is illustrated suitable circuitryfor use in the system of FIG. 3. FIG. 4 illustrates in schematic formthe construction of the inverter 51 of FIG. 3. The DC voltage from therectifier and filter 50 is applied along lines 64 and 65 across a bridgecircuit including four NPN transistors 66, 67, 68 and 69. The transistor66 is connected to the line 64 through a first winding 70 of atransformer T and a diode 71. The base of the transistor 66 is connectedto its emitter through a resistor 72 and a second winding 73 of thetransfonner T The emitter of the transistor 66 is also connected to oneend of the control winding 52 of the parametric inductor 53. This pointis also connected through a diode 74 to the collector of the transistor67. The base of the transistor 67 is connected to its emitter through aresistor 75 and a first winding 76 of a transformer T The emitter isalso connected to the line 65.

The other two arms of the bridge are formed in a similar manner. Thecollector of the transistor 68 is connected to the line 64 through asecond winding 77 on the transformer T and a diode 78. The base of thetransistor 68 is connected to its emitter through a resistor 79 and athird winding 80 on the transformer T The emitter of the transistor 68is also connected to the other side of the control winding 52 of theparametric inductor 53. This latter point is also connected through adiode 80 to the collector of the transistor 69. The base of thistransistor is connected through a resistor 81 and a third winding 82 onthe transformer T,. Each of the arms of the bridge are shunted by adiode. The polarity of the various windings of the transformers T, and Tare indicated by the appropriate dots.

As will be understood by those skilled in art, the transistors 66 and 69and the transistors 68 and 67 are provided with a regenerative or demandtype positive feedback system, i.e., one that is not dependent on anexternal circuit once it is initially triggered and consequently takesless power drive and removes non-symmetrical characteristics. Assumingthat a pulse is applied to the primary winding of the transformer T, avoltage will be induced in the secondary winding 73 with the result thatthe base-emitter bias of the transistor 66 will be increased and thetransistor will begin to conduct. Similarly, the transistor 69 willbegin to conduct with the result that a current passes through thesecondary winding 70 of transformer T, the diode 71, the transistor 66,the control winding 52 of the parametric inductor 53, the diode 80 andthe transistor 69. Passage of current through the winding 70 of thetransformer T, will cause a greater voltage to be induced in the winding73 and 82 with the result that the transistor 66 and 69 will increaseconduction. This regeneration will continue until the demand from thecontrol winding 52 of the inductor 53 decreases.

In this regard, it must be remembered that the operation of theparametric inductor 53 is bilateral, that :is, a change in the currentpassing through the load winding 54 will effect the self-inductance ofcontrol winding 52in the same manner that a current passing through thecontrol winding 52 will eflect self-inductance of the load winding 54.Thus, when the inductance of the control winding 52 begins to increase,a point will be reached when its impedance causes the current flowingthrough the circuit previously described to decrease with the resultthat the transistors 66 and 69 will eventually become non-conducting. Ofcourse, the transformer T, must be designed so that it will stay onuntil triggered off, that is, the time constant of the transformercircuit (i.e., the length of time positive regeneration can take place)must be greater than the period at which the parametric circuit is tooperate. The circuit including the transistors 68 and 67 operates in thesame fashion through the transformer T, and drives a current through thecontrol winding 52 of the parametric inductor 53 in the oppositedirection so that an alternating current is delivered to the controlwinding.

As pointed out previously, it is necessary for efficient and safeoperation that the transistors 66 and 69 be cutoff before thetransistors 68 and 67 become conductive and vice-versa. As has also beenexplained, it is desirable to introduce a time delay between cut-off ofone set of transistors and cut-on of the other set because of the slowresponse time of conventional transistors and the desirability of usingthe latter for reasons of economy. FIG. 5 illustrates a circuit suitablefor controlling the triggering on and off of the transistors in theinverter circuit of FIG. 4.

As illustrated in FIG. 5, the transformer T has two primary windings 83and 84, the windings being poled in opposite directions so that when acurrent passes through the winding 83 the transistors 66 and 69 will berendered conducting and when a current passes through the winding 84,the transistors will be rendered non-conducting. Similarly, thetransfonner T, has two primary windings 85 and 86 which are also poledin opposite directions and which serve to trigger the transistors 68 and67 on and off respectively.

As shown in FIG. 5, the variable frequency drive and delay logic circuit60 includes a flip-flop 87 which receives the output of the controlamplifier and oscillator 59 and alternately produces a pulse at its Aand A output in response thereto. As will be recalled, the frequency orrepetition rate of the pulses from the control amplifier and oscillator59 is dependent upon the magnitude of the voltage appearing across theoutput terminals 57 and 58. The pulses from the control amplifier andoscillator 59 are also fed to the input of a one shot multivibrator 88which produces a zero output at the output M in response thereto for atime determined by a time constant circuit comprising a capacitor 89 anda variable resistor 90, the resistor being variable in order to vary thetime constant. The output M of the multivibrator 88 is applied to afirst input of a NAND gate 91, the other input of this gate beingconnected to the output A of the flip-flop 88. The output M ofmultivibrator 88 is also applied to a second NAND gate 92, the otherinput of which is connected to the A output of the flip-flop 87. Theoutput of the NAND gate 91 is applied through a resistor 93 to the baseof a transistor 94 connected in circuit with the primary winding 83 ofthe transformer T, and biased by a base resistor 95.

The output of the NAND gate 91 is also fed to an inverter 96, the outputof which is connected through a resistor 97 to the base of a transistor98 which is connected in circuit with the primary winding 84 of thetransformer T, and which is biased by a resistor 99. Theemitter-collector path of the transistor 94 is shunted by a diode 100.Similarly, the collector-emitter path of the transistor 98 is shunted bya diode 101.

The output of the NAND gate 92 is coupled through a resistor 108 to thebase of a transistor 109 which is connected in circuit with the primarywinding of the transformer T The output of the NAND gate 92 is alsoconnected to an inverter 107 whose output is coupled through a resistorto the base of a transistor 106 which is connected in series with theprimary winding 86 of transformer T Transistors 106 and 109 are biasedby resistors 110 and 111 respectively and have their collector-emitterpaths shunted by diodes 112 and 113. For ease in discussion the outputof the NAND gate 91 will be referred to as H, the output of the inverter96 as H, the output of the NAND gate 92 as G, and output of the inverter107 as G, reference being made to these outputs on the timing diagram ofFIG. 6.

It is believed that the operation of the circuits of FIGS. 4 and 5 willbe apparent to those skilled in the art, particularly when viewed withthe timing diagram of FIG. 8. When a pulse C is received from thecontrol amplifier and oscillator 59, assume that the flip-flop 87produces an output pulse at the output A but not at the output A. Ofcourse, the next pulse C will reverse this relationship. The pulse C,.will also cause the multivibrator 88 to produce a pulse at the output ifafter a delay that is determined by the parameters of the capacitor 89and resistor 90 of the time constant network.

Assume that the transistors 66 and 69 of FIG. 4 are conducting when theaforementioned pulse Cp is received by the flip-flop 87. Since there isnow no signal at either input of the NAND gate 91, its outputimmediately goes positive with the result that the transistor 94 isrendered conductive and a current passes through the primary winding 83of the transformer T, This current in the primary winding 83 poled asshown causes a current to be induced in the secondary windings 70, 73and 82 in a direction opposite to the current that was previouslyflowing therein with the result that the transistors 66 and 69 are cutoff. Because of the characteristics of these transistors, as previouslymentioned, they w ll continue to conduct for some period after thetriggering signal is received.

Upon the occurrence of a pulse at the output H of the multivibrator 88,the NAND gate 92 sees coinciding inputs and consequently the inverter107 puts out a positive output pulse a This pulse causes the transistor106 to be rendered conductive with the result that a current passesthrough the primary winding 86 of the transformer T This causes acurrent to be induced in the secondary windings 77, 80 and 76 of thetransformer T with the result that the transistors 68 and 67 arerendered conductive. On the occurrence of the next pulse C the flip-flop87 will produce a positive pulse at output A and a zero atoutput A.Accordingly, the output of the NAND gate 92 goes to zero and applies apositive pulse to the base of the transistor 109 causing it to becomeconductive and turning off the transistors 68 and 67.

The NAND gate 91 operates similarly to the NAND gate 92. Consequently, ashort time after the transistors 68 and 67 are turned off, the timedepending on the time constant of the network 89, 90, the output H ofthe NAND gate 91 will go to zero with the result that the output H ofthe inverter 96 goes positive, the transistor 98 is biased intoconduction, current flows through the primary winding 84 of thetransformer T inducing a current in the secondary windings 70, 73, and82 of the transformer T and causing the transistors 66 and 69 to beginconduction.

When the next pulse C is received by the flip-flop 87, the output of theflip-flop will switch from A to A with the result that the output H ofthe NAND gate 91 will immediately go positive. This causes thetransistor 94 to be biased into conduction and the transistor 98 to beturned off. Current flowing through the winding 83 of the transformer Tas a result of the conduction of the transistor 94 induces a current inthe windings 70, 73 and 82 of the transformer T in a direction such thatthe transistors 66 and 69 are switched off. This operation continues,the frequency at which the transistors 66, 69 and 68, 67 are switchedbeing dependent upon the voltage developed across the output terminals57 and 58 of FIG. 3.

From the foregoing description, it can be seen that a highly accurate,inexpensive, simple, and highly efficient voltage regulator has beenprovided. It should be understood that the broad principles of theinvention do not require the use of the p articular control circuitryillustrated, these illustrations being only for the purposes of clarity.The present embodiments of the invention are therefore to be consideredin all respects as illustrative and not restrictive.

What is claimed is:

1. A voltage regulator comprising:

terminal means for connection to a source of unregulated voltage;

an inverter coupled to said terminal means for producing output pulseshaving a frequency higher than the frequency of said unregulatedvoltage, said inverter comprising first and second conducting meansadapted to be alternately caused to conduct or not conduct;

a parametric device employing an inductor comprising a load winding oncore means, a capacitor, means connecting said inductor and saidcapacitor in an energy storing tank circuit, and means for varying theself-inductance of said inductor at twice the frequency of the output ofthe inverter, said means comprising a control winding wound on saidmeans such that flux from said control winding does not cut said loadwinding and coupled to said inverter, said parametric device providingcomplete isolation of the output from the control winding, the outputwaveform being determined by the tank circuit;

Y an output circuit coupled to said tank circuit for delivering anoutput voltage;

first means coupled to said output circuit for producing pulses having arepetition rate corresponding to the magnitude of said output voltage;

logic circuit means coupled to said first means and to said inverter foralternately causing said first and second conducting means to conduct ornot conduct in response to said pulses from said first means, said logiccircuit means comprising signal producing means for producing a firstsignal-which causes said first conducting means to conduct, a secondsignal which causes said first conducting means to cease conducting, athird signal which causes said second conducting means to conduct and afourth signal which causes said second conducting means to ceaseconducting, and

a one shot multivibrator coupled to receive the pulses from said firstmeans and having a variable time constant network providing delay meansfor delaying the production of said third signal until said firstconducting means have ceased conducting and for delaying said firstsignal until said second conducting means have ceased conducting.

2. A voltage regulator comprising:

terminal means for connection to a source of unregulated voltage;

an inverter coupled to said terminal means for producing output pulseshaving a frequency higher than the frequency of said unregulatedvoltage, said inverter comprising first and second co nlucting meansconsisting of transistors adapted to be alternately caused to conduct ornot conduct;

a parametric device employing an inductor comprising a load winding oncore means, a capacitor, means connecting said inductor and saidcapacitor in an energy storing tank circuit, and means for varying theself-inductance of said inductor at twice the frequency of the output ofthe inverter, said means comprising a control winding wound on saidmeans such that flux from said control winding does not out said loadwinding and coupled to said inverter, said parametric device providingcomplete isolation of the output from the control winding, the outputwaveform being determined by the tank circuit;

an output circuit coupled to said tank circuit for delivering an outputvoltage;

first means coupled to said output circuit for producing pulses having arepetition rate corresponding to the magnitude of said output voltage;

logic circuit means coupled to said first means and to said inverter foralternately causing said first and second conducting means to conduct ornot conduct in response to said pulses from said first means, said logiccircuit means comprising signal producing means for producing a firstsignal which causes said first conducting means to conduct, a secondsignal which causes said first conducting means to cease conducting, athird signal which causes said second conducting means to conduct and afourth signal which causes said second conducting means to ceaseconducting, wherein said signal producing means include first and secondtransformers each having a pair of oppositely poled primary windings anda secondary winding, the secondary winding of each transformer beingcoupled in the base circuit of a corresponding transistor; and

delay means for delaying the production of said third signal until saidfirst conducting means have ceased conducting and for delaying saidfirst signal until said second conducting means have ceased conducting.

3. The regulator of claim 2 wherein said transformers are each providedwith a second secondary winding, said secondary windings being coupledto corresponding transistors to provide said transistors withregenerative feedback.

1. A voltage regulator comprising: terminal means for connection to asource of unregulated voltage; an inverter coupled to said terminalmeans for producing output pulses having a frequency higher than thefrequency of said unregulated voltage, said inverter comprising firstand second conducting means adapted to be alternately caused to conductor not conduct; a parametric device employing an inductor comprising aload winding on core means, a capacitor, means connecting said inductorand said capacitor in an energy storing tank circuit, and means forvarying the self-inductance of said inductor at twice the frequency ofthe output of the inverter, said means comprising a control windingwound on said means such that flux from said control winding does notcut said load winding and coupled to said inverter, said parametricdevice providing complete isolation of the output from the controlwinding, the output waveform being determined by the tank circuit; anoutput circuit coupled to said tank circuit for delivering an outputvoltage; first means coupled to said output circuit for producing pulseshaving a repetition rate corresponding to the magnitude of said outputvoltage; logic circuit means coupled to said first means and to saidinverter for alternately causing said first and second conducting meansto conduct or not conduct in response to said pulses from said firstmeans, said logic circuit means comprising signal producing means forproducing a first signal which causes said first conducting means toconduct, a second signal which causes said first conducting means tocease conducting, a third signal which causes said second conductingmeans to conduct and a fourth signal which causes said second conductingmeans to cease conducting, and a one shot multivibrator coupled toreceive the pulses from said first means and having a variable timeconstant network providing delay means fOr delaying the production ofsaid third signal until said first conducting means have ceasedconducting and for delaying said first signal until said secondconducting means have ceased conducting.
 2. A voltage regulatorcomprising: terminal means for connection to a source of unregulatedvoltage; an inverter coupled to said terminal means for producing outputpulses having a frequency higher than the frequency of said unregulatedvoltage, said inverter comprising first and second conducting meansconsisting of transistors adapted to be alternately caused to conduct ornot conduct; a parametric device employing an inductor comprising a loadwinding on core means, a capacitor, means connecting said inductor andsaid capacitor in an energy storing tank circuit, and means for varyingthe self-inductance of said inductor at twice the frequency of theoutput of the inverter, said means comprising a control winding wound onsaid means such that flux from said control winding does not cut saidload winding and coupled to said inverter, said parametric deviceproviding complete isolation of the output from the control winding, theoutput waveform being determined by the tank circuit; an output circuitcoupled to said tank circuit for delivering an output voltage; firstmeans coupled to said output circuit for producing pulses having arepetition rate corresponding to the magnitude of said output voltage;logic circuit means coupled to said first means and to said inverter foralternately causing said first and second conducting means to conduct ornot conduct in response to said pulses from said first means, said logiccircuit means comprising signal producing means for producing a firstsignal which causes said first conducting means to conduct, a secondsignal which causes said first conducting means to cease conducting, athird signal which causes said second conducting means to conduct and afourth signal which causes said second conducting means to ceaseconducting, wherein said signal producing means include first and secondtransformers each having a pair of oppositely poled primary windings anda secondary winding, the secondary winding of each transformer beingcoupled in the base circuit of a corresponding transistor; and delaymeans for delaying the production of said third signal until said firstconducting means have ceased conducting and for delaying said firstsignal until said second conducting means have ceased conducting.
 3. Theregulator of claim 2 wherein said transformers are each provided with asecond secondary winding, said secondary windings being coupled tocorresponding transistors to provide said transistors with regenerativefeedback.